FIG. 1 is a schematic diagram of a conventional circuit 100 for providing an exclusive NOR function or an AND function. Circuit 100 includes 2-input exclusive NOR (XNOR) gate 104, 2-input AND gate 108, and two-to-one multiplexer 110. XNOR gate 104 is a standard gate which provides a logic exclusive NOR function. AND gate 108 is a standard gate which provides a logic AND function. Both XNOR gate 104 and AND gate 108 receive input signals from lines 120 and 122. XNOR gate 104 provides an output signal on line 126 and AND gate 108 provides an output signal on line 136.
The output signal line 126 of XNOR gate 104 is connected to the "0" input terminal of multiplexer 110. The output signal line 136 of AND gate 108 is connected to the "1" input terminal of multiplexer 110.
The signal on output signal line 114 of multiplexer 110 may be equal to the output signal provided by XNOR gate 104 or the output signal provided by AND gate 108, depending on the status of the select signal on select signal line 118 of multiplexer 110. When the select signal applied to select signal line 118 is in a logic low state (e.g., 0 volts), the signal at the "0" input terminal of multiplexer 110 is supplied to output signal line 114 of multiplexer 110. Conversely, when the select signal applied to select signal line 118 is in a logic high state (e.g., 5 volts), the signal line 118 is in a logic high state (e.g., 5 volts), the signal at the "1" input terminal of multiplexer 110 is supplied to output signal line 114 of multiplexer 110. Accordingly, a select signal having a logic low state causes circuit 100 to implement an exclusive NOR function, and a select signal having a logic high state causes circuit 100 to implement an AND function.
FIG. 2 is a schematic diagram of XNOR gate 104 of FIG. 1, which is implemented using four transistors. XNOR gate 104 includes inverter 144 (which requires two transistors) and two transistors 150 and 154. Output signal line 126 connects to input terminal "0" of multiplexer 110 (FIG. 1).
FIG. 3 is a schematic diagram of AND gate 108 of FIG. 1, which is implemented using six transistors. AND gate 108 is formed by inverting the output of a standard NAND gate with an inverter (a NOT gate). Accordingly, AND gate 108 includes six transistors 162, 164, 166, 168, 170 and 172. Output signal line 136 connects to input terminal "1" of multiplexer 110 (FIG. 1).
A standard implementation of circuit 100 as described above requires a significant number of transistors (i.e., 10 transistors for XNOR gate 104 and AND gate 108, and approximately four transistors for the implementation of multiplexer 110). Therefore, it would be desirable to have a logic circuit which is programmable to provide either an exclusive NOR function or an AND function and which requires fewer transistors than circuit 100.
FIG. 4 is a schematic diagram of a conventional circuit 180 for providing an exclusive OR function or an OR function. Circuit 180 includes 2-input OR gate 184, 2-input exclusive OR (XOR) gate 190, and two-to-one multiplexer 110. Fourteen transistors are typically required to implement circuit 180. More specifically, six transistors are required to implement OR gate 184, four transistors are required to implement XOR gate 190, and four transistors are required to implement 2-to-1 multiplexer 110. The implementation of logic circuit 180 therefore requires a significant number of transistors. It would therefore be desirable to have a logic circuit which is programmable to provide either an OR function or an exclusive OR function and which requires fewer transistors than circuit 180.